Verification Guide

SystemVerilog NonBlocking assignment

Nonblocking assignment.

  • non-blocking assignment statements execute in parallel
  • In the non-blocking assignment, all the assignments will occur at the same time. (during the end of simulation timestamp)

Nonblocking assignment example

In the below example, a and b are initialized with values 10 and 15 respectively, after that b is being assigned to a (a value will become 15), and value 20 is assigned to b. After assignment values expected in a and b are 15 and 20 respectively. but these values will get assigned only after the simulation time-stamp.

Simulator Output:

systemverilog non blocking assignment in task

Nonblocking assignment example-2

In the below example, a and b are initialized with value 10 and 15 respectively. x<=a+b and y<=a+b+x value of x is sum of a (10) and b (15). -> x=10+15=25. value of y is sum of a (10) ,b(15) and x (0) -> became at current simulation time-stamp value of x=0. new value will get assigned at the end of current time stamp, and new value will be available only after the current time-stamp). therefore y=10+15+0=25;

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Verilog Blocking & Non-Blocking

Blocking assignment statements are assigned using = and are executed one after the other in a procedural block. However, this will not prevent execution of statments that run in a parallel block.

Note that there are two initial blocks which are executed in parallel when simulation starts. Statements are executed sequentially in each block and both blocks finish at time 0ns. To be more specific, variable a gets assigned first, followed by the display statement which is then followed by all other statements. This is visible in the output where variable b and c are 8'hxx in the first display statement. This is because variable b and c assignments have not been executed yet when the first $display is called.

In the next example, we'll add a few delays into the same set of statements to see how it behaves.

Non-blocking

Non-blocking assignment allows assignments to be scheduled without blocking the execution of following statements and is specified by a symbol. It's interesting to note that the same symbol is used as a relational operator in expressions, and as an assignment operator in the context of a non-blocking assignment. If we take the first example from above, replace all = symobls with a non-blocking assignment operator , we'll see some difference in the output.

See that all the $display statements printed 'h'x . The reason for this behavior lies in the way non-blocking assignments are executed. The RHS of every non-blocking statement of a particular time-step is captured, and moves onto the next statement. The captured RHS value is assigned to the LHS variable only at the end of the time-step.

So, if we break down the execution flow of the above example we'll get something like what's shown below.

Next, let's use the second example and replace all blocking statements into non-blocking.

Once again we can see that the output is different than what we got before.

If we break down the execution flow we'll get something like what's shown below.

systemverilog non blocking assignment in task

IMAGES

  1. Mastering Blocking & Non-Blocking Assignments, Loop Statements, and Jump Statements

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  2. Swapping the values by blocking and non-blocking assignment in #verilog #systemverilog #uvm #cmos

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  3. Non-Blocking Socket Communication in SystemVerilog Using DPI-C

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  4. SystemVerilog Tutorial in 5 Minutes 16a

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  5. Non-Blocking Assignment

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  6. PPT

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VIDEO

  1. SoC Episode 5 Monitor and IRQs

  2. Blocking vs Non-blocking Assignment Statements

  3. COSE221

  4. ENG104

  5. Unpaid Debt

  6. TASK 1